Instrumentation

Charge Readout ASIC

Our group works on the development of Application Specific Integrated Circuits (ASICs) for charge readout which plays a crucial role in the nEXO experiment, aiming to refine the detection and analysis of charge signals emanating from charge tiles. These ASICs, designed to operate efficiently in cryogenic conditions, are integral to a system that encompasses approximately 4,000 channels distributed across roughly 120 charge modules, each hosting 32 channels. The primary function of these ASICs involves the amplification, digitization, and multiplexing of charge signals, which are then relayed through transition boards situated within transition boxes inside the water tank, ultimately reaching the Data Acquisition (DAQ) system via optical fiber. This intricate setup is engineered to distinguish between single and multiple scatter events within nEXO, a critical factor for achieving high granularity in the charge detector and optimizing energy resolution near the Q-value. The design prioritizes the reduction of electronic noise per channel, the minimization of intrinsic radiation through reduced cabling and the use of clean fused silica, all while ensuring the longevity of the electronics.

Fused Silica ASIC Board

The ASIC-board within our national lab's charge readout system serves as a critical intermediary, channeling signals from the charge tiles into the ASIC while effectively decoupling noise from the ASIC's power planes. It further distributes power and data signals to and from the ASIC via cable connections to the Data Acquisition (DAQ) system. Constructed from fused silica, the board is designed with evaporated traces, vias, and surface mount pads for components, facilitating a compact and efficient layout. Wire bonds create vital connections from the charge tile to the ASIC board and from the board's traces to the ASIC itself, ensuring seamless signal transmission and power distribution within a 5 x 5 cm² area.

The choice of fused silica for the ASIC board is strategic, leveraging the same production technology developed for the anode charge tiles, which underscores our lab's commitment to consistency and innovation in material choice. This technology supports a three-layer board design, incorporating power/ground split planes and dual routing layers to optimize signal integrity and minimize electronic noise. The ASIC board's design, devoid of through-quartz vias (TQVs) for simplicity, maintains the mechanical robustness required to bridge the anode backplane and charge tiles, all while adhering to strict requirements for minimizing intrinsic background radiation.

Transition Board

In the intricate architecture of our charge readout system, the transition boards play a pivotal role, strategically positioned between the ASIC boards and the Data Acquisition (DAQ) readout board. These boards are engineered to fulfill several critical functions: they supply power, facilitate the transmission of control signals to the ASICs, and serve as conduits for data flowing from the ASICs to the readout and timing systems. Each board is designed to interface with the DAQ system, supporting connections to 30 tiles, thereby playing a key role in the experiment's data management infrastructure.

One of the strategic decisions in the design of the transition boards was to locate them within the water tank, despite the challenges this presents for serviceability. This placement was chosen to leverage the advantages of proximity to the ASICs such as delivering low-noise power, efficient recovery of data signals, and the provision of high-quality clock signals, essential for maintaining the integrity and reliability of data transmission. The use of high reliability components ensures that the boards can perform their essential functions with minimal intervention, addressing the unique challenges posed by their critical position in the system's architecture.